Generally, television receivers are provided with a circuit for generating a clock signal in synchronization with a television synchronizing signal. The television synchronizing signal is supplied from a tuner circuit in the television receiver. Recently, the typical clock signal generating circuit has been constituted by a phase-locked loop (referred as PLL hereafter) circuit configuration.
Referring now to FIG. 1, an example of the conventional PLL clock signal generating circuit for a television receiver will be described. FIG. 1 is a block diagram showing the conventional circuit of the PLL clock signal generating circuit.
In FIG. 1, a phase comparator 10, a reference voltage supply circuit 12, a low-pass filter (referred as LPF hereafter) 14, a voltage controlled oscillator (referred as VCO hereafter) 16 and a frequency divider 18 are connected into a loop circuit so that the PLL clock signal generating circuit 20 is constituted. That is, an output terminal 10a of phase comparator 10 is coupled to an input terminal 16a of VCO 16. An output terminal 16b of VCO 16 is coupled to an input terminal 18a of frequency divider 18. An output terminal 18b of frequency divider 18 is coupled to a first input terminal 10b of phase comparator 10. Reference voltage supply circuit 12 and LPF 14 are parallelly connected between the output terminal 10a of phase comparator 10 or input terminal 16a of VCO 16 and a ground terminal 22.
Reference voltage supply circuit 12 is comprised of a resistor 122 and a DC voltage source 124, which are connected in series. Resistor 122 serves to set the loop gain of the PLL clock signal generating circuit 20. DC voltage source 124 supplies a reference voltage VB to VCO 16. The reference voltage VB sets the oscillation frequency F0 of VCO 16 to a prescribed center oscillation frequency Fc.
VCO 14 is comprised of a resistor 142 and a capacitor 144 which are connected in series. Resistor 142 and capacitor 144 set the filter characteristics of VCO 14. Accordingly, VCO 14 takes out an AC component imposed on S10, which leaks from Sc through phase comparator 10, with the filter characteristics.
Phase comparator 10 is further provided with second and third input terminals 10c and 10d. First input terminal 10b is provided for receiving a fed-back signal from frequency divider 18. Second input terminal 10c and third input terminal 10d are provided for receiving a composite synchronizing signal Sc and a masking signal Sm, respectively, from a conventional tuner section (not shown) of a television receiver.
The composite synchronizing signal Sc is comprised of at least two partial signals, e.g., a horizontal synchronizing signal Sh and a vertical synchronizing signal Sv. Typically, the composite synchronizing signal Sc further includes an equalizing signal Se. Masking signal Sm is a pulse signal corresponding to the period of the vertical synchronizing signal Sv or the period of the equalizing signal Se and the vertical synchronizing signal Sv.
The output signal of PLL clock signal generating circuit 20 is an oscillation output S16 from output terminal 16b of VCO 16. Oscillation signal S16 has the center frequency Fc, which is N (a positive integer) times the frequency Fh of horizontal synchronizing signal Sh. In an NTSC system television receiver, Fh is 15.75 KHz. Further, for example, the value of N is set to 2,048. Thus, PLL clock signal generating circuit 20 generates a clock signal with a frequency of 32,256 MHz. The clock signal generated by PLL clock signal generating circuit 20 is conventionally used for clock control of various digital circuits in the television receiver.
The frequency Fo of the oscillation signal S16 is divided to 1/N by frequency divider 18, so that the fed-back signal S18 from frequency divider 18 has the same frequency Fh as the horizontal frequency Fh of the horizontal synchronizing signal Sh in the composite synchronizing signal Sc.
Phase comparator 10 compares the phases of the fed-back signal S18 and the composite synchronizing signal Sc supplied to first input terminal 10b and second input terminal 10c, respectively. However, the operation of phase comparator 10 is masked during the period of equalizing signal Se and vertical synchronizing signal Sv by masking signal Sm supplied to third input terminal 10d, so that phase comparator 10 actually compares the phase Ph of horizontal synchronizing signal, Sh with the phase P18 of fed-back signal S18. Phase comparator 10 outputs a phase error signal S10 as a DC current in response to a phase error .DELTA.P between Ph and P18.
Phase comparator 10 is comprised of a phase error detection circuit 102, a current supply source 104 and a current extraction source 106. Phase error detection circuit 102 activates current supply source 104 when fed-back signal S18 delays in phase in comparison to horizontal synchronizing signal Sh. Current supply source 104 supplies a DC current to input terminal 16a of VCO 16. The DC current flows into capacitor 144. Capacitor 144 has been previously charged to reference voltage VB by DC voltage source 124 in reference voltage supply circuit 12. As a result, the voltage VA of input terminal 16a of VCO 16 becomes higher than VB.
Phase error detection circuit 102 activates current extraction source 106 when fed-back signal S18 advances in phase in comparison to horizontal synchronizing signal Sh. Current extraction source 106 extracts a DC current from input terminal 16a of VCO 16. The extraction of the DC current reduces the charge of capacitor 144, so that the voltage VA on input terminal 16a becomes lower than VB.
The voltage VA caused by the current supply or the current extraction operates to adjust the frequency Fo of the oscillation signal S16 of VCO 16 to the prescribed center frequency Fc.
Both current supply source 104 and current extraction source 106 are deactivated when phase error .DELTA.P is zero. At this time, voltage VA is equal to reference voltage VB, so that VCO 16 oscillates at the prescribed center frequency Fc.
As mentioned above, the oscillation frequency Fo of oscillation signal S16 output from VCO 16 varies in response to voltage VA. The variation of the oscillation frequency Fo is negatively fed-back to phase comparator 10 through frequency divider 18. As a result, the oscillation frequency Fo of PLL clock signal generating circuit 20 is servo-controlled, so as to restore the prescribed center frequency Fc if the frequency the oscillation frequency Fo is disturbed by various factors, such as a temperature change.
This conventional clock signal generating circuit for a television receiver has a drawback, as described below.
The operation of phase comparator 10 is masked by masking signal Sm for the periods corresponding to equalizing signal Se and vertical synchronizing signal Sv, as mentioned above. The masking operation for phase comparator 10 is to prevent a malfunction of phase comparator 10 due to equalizing signal Se and vertical synchronizing signal Sv. If the PLL clock signal generating circuit 20 operates during the periods of equalizing signal Se and vertical synchronizing signal Sv, phase comparator 10 responds to undesired signals, i.e., equalizing signal Se and vertical synchronizing signal Sv, not but to the desired signal, i.e., horizontal synchronizing signal Sh. As a result, the oscillation frequency Fo of oscillation signal S16 output from the PLL clock signal generating circuit 20 varies enormously to follow the frequency of equalizing signal Se or vertical synchronizing signal Sv. However, a malfunction of the PLL clock signal generating circuit 20 is prevented by masking signal Sm. The idea of masking phase comparator 10 for the period of equalizing signal Se and vertical synchronizing signal Sv is described in Japanese Patent Disclosure No. P 61-145969, the disclosure of which is hereby incorporated by reference.
Masking signal Sm deactivates phase comparator 10 for the period Tm of equalizing signal Se and vertical synchronizing signal Sv. In other words, phase comparator 10 is disconnected from reference voltage supply circuit 12, VCO 14 and VCO 16 during the masking period Tm. If voltage VA on input terminal 16a of VCO 16 differs from reference voltage VB just before the masking operation, voltage VA gradually approaches the reference voltage VB.
The variation of voltage VA will be described in detail below, in reference to FIG. 2. FIG. 2 is a graph showing the variation of voltage VA. The horizontal axis of the graph is a time axis. On the time axis, ta and tb represent starting and ending times of the masking period Tm. The vertical axis of the graph shows the amounts of voltage VA and the reference voltage VB.
Voltage VA is charged on capacitor 144 in LPF 14. If voltage VA has a value VAh, which is higher than reference voltage VB (VA&gt;VB), just before the masking operation, voltage VA has the value VAh at the starting time ta. Voltage VA then decreases from the value VAh towards the reference voltage VB. This is because voltage VA is discharged through resistors 142, 122 and DC voltage source 124. The variation of voltage VA in this case is shown by Graph Gh. The discharge is carried out at a relatively slow rate based on a large time constant TCa, which is defined by the resistances R142, R122 of resistors 142, 122 and the capacitance C144 of capacitor 144. The time constant TCa for the discharge operation is expressed as follows: EQU TCa=(R142+R122).multidot.C144
Therefore, voltage VA decreases gradually for the masking period Tm, as shown by a portion Gha of Graph Gh.
When the ending time tb has been reached, phase comparator 10 is activated. That is, phase comparator 10 is again connected to reference voltage supply circuit 12, LPF 14 and VCO 16. Therefore, capacitor 144 in PLL 14 is charged by the DC current supplied from current supply source 104 in phase comparator 10. The capacitor 144 is charged at a relatively fast rate according to a small time constant TCb, which is defined by the resistance R142 of resistor 142 and the capacitance C144 of capacitor 144. The time constant TCb for the charge operation is expressed as follows: EQU TCb=R142.multidot.C144
Voltage VA then increases to the value VAh very fast just after the ending time tb, as shown by a portion Ghb of Graph Gh.
After voltage VA has reached the value VAh, voltage VA is maintained around the value VAh, as shown by a portion Ghc of Graph Gh.
On the contrary, if voltage VA has a value VAl, which is lower than reference voltage VB (VA&lt;VB), just before the masking operation, voltage VA has the value VAl at the starting time ta. Voltage VA then increases from the value VAl towards the reference voltage VB. This is because the DC current supplied from DC voltage source 124 is charged into capacitor 144 through resistors 122 and 142. The variation of voltage VA in this case is shown by Graph Gl. The charge is carried out at the time constant TCa. Therefore, voltage VA increases gradually for the masking period Tm, as shown by a portion Gla of Graph Gl.
When the ending time tb has come, phase comparator 10 is activated. That is, phase comparator 10 is again connected to reference voltage supply circuit 12, PLL 14 and VCO 16. Therefore, current extraction source 106 of phase comparator 10 extracts the DC current from input terminal 16a of VCO 16. The current extraction is carried out by the discharge of capacitor 144 in PLL 14. The discharge is carried out at the time constant TCb. Therefore, voltage VA then decreases to the value VAl very fast just after the ending time tb, as shown by a portion Glb of Graph Gl.
After voltage VA has reached the value VAl, voltage VA is kept around the value VAl, as shown by a portion Glc of Graph Gh.
As mentioned above, voltage VA changes to the value VAh or VAl very fast, after the masking operation has been completed. However, VCO 16 cannot follow such a very fast change of voltage VA at the time when the masking operation has finished. As a result, the oscillation frequency Fo of the PLL clock signal generating circuit 20 becomes unstable. This adversely affects the operation of PLL clock signal generating circuit 20 for generating stable clock signals.